The present invention is related to systems and methods for data synchronization, and more particularly to systems and methods for timing recovery in relation to a data set.
Many baseband and carrier-modulated communication systems utilize timing recovery circuits to synchronize to an available data stream. Such timing recovery circuits operate to recover a clock signal at the symbol rate that is both phase-locked and frequency-locked to the available data stream. As one particular example, a typical read channel employed in a hard disk drive may use a digital phase lock loop circuit as a timing recovery circuit to synchronize to a data stream retrieved from a magnetic storage medium associated with the hard disk drive. Such read channel devices serve as interfaces between a magnetic storage medium on which digital information is stored and external devices (e.g., Central Processing Unit (CPU)) that receive and process the digital information in various applications. Read channel devices take the analog information stored as magnetic pulses on the hard disk drive and convert that information into digital values (i.e., “1”s and “0”s) that are readable by digital devices, such as a CPU.
An example of a digital phase lock loop circuit 100 that may be used to perform timing recovery in read channel is depicted in FIG. 1. Turning to FIG. 1, digital phase lock loop circuit 100 includes a multiplier 105 which receives an error signal (E_N) and a slope (SLOPE) signal from a Viterbi detector. Multiplier 105 produces a phase error signal (PE) at its output. The phase error signal is provided as an input to both a multiplier 110 and a multiplier 115. Multiplier 110 has a frequency gain input (FREQ GAIN) signal, and multiplier 115 has a phase gain (PHASE GAIN) signal input. The output of multiplier 110 is provided to a summation circuit 120, and the output of multiplier 115 is provided to an adder 125. Summation circuit 120 aggregates the output of multiplier 110 and an output from a frequency register 130, and provides the aggregate back to frequency register 130. The output of frequency register 130 and the output of multiplier 115 are added together. The output of adder 125 is provided to a summation circuit 135. Summation circuit 135 aggregates the output of adder 125 and an output from a phase register 140, and provides the aggregate back to phase register 140. The output of phase register 140 is provided to a phase mixer 145 that provides an output signal to control a voltage controlled oscillator.
It is important that read channel devices have the ability to perform timing recovery at reasonably low signal-to-noise ratios. Where, however, the signal-to-noise ratio decreases too far, the read channel will experience an inability to recover a clock and/or an inability to maintain a lock condition. This inability renders the read channel unable to track an incoming waveform and provide accurate estimates of the sampling clock. In some existing read channels, the ability of the timing recovery circuit is stretched to its limits with the current signal-to-noise ratios. Further, the signal-to-noise ratio in many implementations continues to decrease due to, for example, proposed changes in data density and power considerations.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for timing recovery.